1+4 innovation landing domestic EDA tools breakthrough upgrade



EDA (Integrated circuit Design Tool) has developed to this day, and the point and surface tools have been very mature. Does this mean that there are not many opportunities for domestic newcomers? In fact, this is not the case, because traditional tools gradually form current products in its iterative development process, which may not be optimal in terms of efficiency and methods. This is where latecomers without historical baggage can exert their efforts.

EDA (Integrated Circuit Design Tool) has developed to this day, and the point and surface tools have been very mature. Does this mean that there are not many opportunities for domestic newcomers? In fact, this is not the case, because traditional tools gradually form current products in its iterative development process, which may not be optimal in terms of efficiency and methods. This is where latecomers without historical baggage can exert their efforts.

Take the key verification in the chip design process as an example, the existing tools have many pain points. Xinhuazhang Technology Chairman and CEO Wang Libin pointed out that there are currently three pain points in this link:

1. The tool lacks compatibility. Although each tool can solve the corresponding problem, because the algorithm engine cannot effectively interact and share, it is impossible to achieve interconnection and mutual feedback, so many times the chip research and development is re-creating wheels, and even using different tools. After verification, the results were not consistent.

2. Fragmentation of data. It reduces the possibility of verification reuse, making it more difficult to debug and analyze the results and verify the convergence. For example, in the verification process of a chip that lasts for 1-2 years, more than one tool is often used, and each tool can produce verification Coverage rate, but converged and shared coverage rate has been difficult to achieve. Under the influence of fragmentation, the general consensus in the industry is that the time wasted for incentive transplantation, repeated compilation, and fragmented debugging in digital verification accounts for more than 30% of the total verification time.

3. Lack of innovation in tools. The current mainstream tools have gone through the development of the past ten or twenty years and have accumulated outdated technical baggage. These technical baggages make it difficult for tools to integrate with advanced technologies such as artificial intelligence and cloud native. More importantly, the platform formed by the combination of these tools In fact, there is no overall consideration from the beginning of the architecture, so it is difficult to integrate and provide a comprehensive solution that is compatible with each other.

These are all obstacles to the pursuit of faster, stronger, and simpler chip design, and also a major obstacle to the industry’s choice of localized tools. Therefore, the EDA technology of new enterprises must be fully advanced, innovate on the underlying framework, support multiple processor architectures; support cloud native, artificial intelligence and other technologies; most importantly, must be innovative in methodology.

Indeed, verification occupies a lot of time and cost. TC.Lin, the chief scientist of Xinhua Zhang, quoted an IBS report and pointed out that the cost of chip design is mainly two pieces: functional verification and software development. Among them, the bottleneck of verification affects the entire design cycle-before the pre-requirement definition and RTL synthesis, a complete verification of the high-level design is required; after the RTL is written, the final circuit is generated through synthesis and placement and routing, and Both of these tools may also cause functional errors, so verification must be done again; after the chip is taped out, it is necessary to make sure that all the processes meet the design requirements, and post-silicon (post-silicon) verification is required. The whole process is time consuming and laborious.

In order to reduce the cost of verification, the industry has adopted software and hardware co-verification to shorten the development cycle, that is, shift-left, the verification method in the chip design process, including system and chip, hardware and software. But this is not enough to solve the problem of high design cycle and cost. TC.Lin said that since the establishment of Xinhuazhang, in addition to the development of mainstream verification tools, it has also continued to pay attention to research and find ways to solve the above-mentioned dilemma. In the EDA 2.0 white paper released by the company, three key paths are proposed: openness and standardization, automation, intelligence, platform and service.

Recently, Xinhua Zhang has launched the latest product portfolio, which embodies several elements mentioned in the critical path of the white paper. This group of products includes a groundbreaking smart V verification platform and four new architecture EDA verification tools:

FusionVerify Platform

1+4 innovation landing domestic EDA tools breakthrough upgrade

It consists of five product series including logic simulation, formal verification, smart verification, FPGA prototype verification system and hardware simulation system, and three bases including smart compilation, smart debugging and smart verification cockpit.

The Smart V verification platform has a unified debugging system, a compilation system, an intelligent segmentation technology, a rich scene incentive source, and a unified cloud-native software architecture. It can integrate different tool technologies and provide customization for various designs and different scenarios. The comprehensive verification solution that solves the current industry compatibility challenges of individual tools and verification efficiency challenges caused by data fragmentation. Smart V verification platform can effectively improve verification efficiency and ease of use of the solution, and bring verification benefits that cannot be provided by point tools.

Huajie (HuaPro-P1)
High-performance FPGA prototype verification system

1+4 innovation landing domestic EDA tools breakthrough upgrade

Based on FPGA hardware and full-process software with independent intellectual property rights, it can help SoC/ASIC chip customers realize the automatic synthesis, segmentation, optimization, wiring and debugging of design prototypes, and can automatically realize the intelligent design process, effectively reducing user manual input and shortening the chip The verification cycle provides a new generation of intelligent pre-silicon verification system with large capacity, high performance, automatic implementation, debuggability, and high availability for system verification and software development.

Dome (GalaxSim-1.0)
Digital simulator

1+4 innovation landing domestic EDA tools breakthrough upgrade

Use the new software architecture to provide multi-platform support, support different processor computing platforms, such as X86, ARM, etc., and have been tested on multiple domestic architectures based on the ARM platform. It can be combined with the universal debugger and universal coverage database of the Xinhuazhang’s Dome GalaxPSS intelligent verification system, and the Dome simulator can efficiently cooperate with other verification tools to provide a unified data interface. It supports IEEE1800 SystemVerilog grammar, IEEE1364 Verilog grammar, and IEEE1800.2 UVM methodology. It has reached the level of mainstream commercial simulators in terms of semantic analysis, simulation behavior, and timing models.

Dome (GalaxPSS)
A new generation of intelligent verification system

1+4 innovation landing domestic EDA tools breakthrough upgrade

Based on the fusion of Accellera PSS standard and advanced verification methodology, for current and future complex verification scenarios, scenarios are automatically generated, reducing the reliance on the experience of engineers manually writing scenarios, generating more efficient test scenarios and test incentives for the chip, and improving verification Scene coverage and completeness. The code generated by PSS is portable, which can ensure that it is suitable for software simulation, hardware simulation, FPGA prototype verification, and even system verification, providing from single-platform verification to multi-platform interactive verification.

Qionghan (GalaxFV)
The domestic EDA field takes the lead in an extensible formal verification tool based on word-level modeling

1+4 innovation landing domestic EDA tools breakthrough upgrade

It adopts high-performance word-level modeling (Word-Level Modeling) method to build, with high performance, high scalability, friendly expansion interface, the model has reached the international advanced level. Equipped with a high-concurrency and high-performance solver, an intelligent scheduling algorithm engine, and a dedicated assertion library, it can make full use of computing power and improve parallel efficiency, while effectively improving ease of use and use efficiency, lowering the threshold for formal verification in the industry .

The future digital system will be a deep integration of system + chip + algorithm + software. In less than two years, Xinhuazhang has developed the above products from scratch, laying a solid foundation for a more intelligent system design process. Wang Libin said that the release of the new platform and products will have far-reaching significance not only for the Xinhua chapter, but also for the entire EDA industry and integrated circuit design industry.

At present, these tools have been used in the chip design of companies such as the Institute of Semiconductors of the Chinese Academy of Sciences, Feiteng, Haiguang, Zhanrui, and ZTE Microelectronics. Ding Wenwu, president of the National Integrated Circuit Industry Investment Fund, said that since its establishment, Xinhuazhang has continued to innovate and forge ahead and has become a new backbone enterprise in the field of digital verification in China. Shen Changxiang, an academician of the Chinese Academy of Engineering, said that Xinhuazhang launched a high-performance integrated circuit design tool with independent intellectual property rights and supporting domestic computer architecture servers within two years of its establishment. R&D work provides more choices and promotes the safer development of the domestic integrated circuit industry chain. Ye Tianchun, National 02 Special Technology Chief, also congratulated Xinhuazhang’s new digital EDA verification product on the market. He also said that for China, the next few years will usher in a great opportunity for the development of domestic EDA tools.

EDA (Integrated Circuit Design Tool) has developed to this day, and the point and surface tools have been very mature. Does this mean that there are not many opportunities for domestic newcomers? In fact, this is not the case, because traditional tools gradually form current products in its iterative development process, which may not be optimal in terms of efficiency and methods. This is where latecomers without historical baggage can exert their efforts.

Take the key verification in the chip design process as an example, the existing tools have many pain points. Xinhuazhang Technology Chairman and CEO Wang Libin pointed out that there are currently three pain points in this link:

1. The tool lacks compatibility. Although each tool can solve the corresponding problem, because the algorithm engine cannot effectively interact and share, it is impossible to achieve interconnection and mutual feedback, so many times the chip research and development is re-creating wheels, and even using different tools. After verification, the results were not consistent.

2. Fragmentation of data. It reduces the possibility of verification reuse, making it more difficult to debug and analyze the results and verify the convergence. For example, in the verification process of a chip that lasts for 1-2 years, more than one tool is often used, and each tool can produce verification Coverage rate, but converged and shared coverage rate has been difficult to achieve. Under the influence of fragmentation, the general consensus in the industry is that the time wasted for incentive transplantation, repeated compilation, and fragmented debugging in digital verification accounts for more than 30% of the total verification time.

3. Lack of innovation in tools. The current mainstream tools have gone through the development of the past ten or twenty years and have accumulated outdated technical baggage. These technical baggages make it difficult for tools to integrate with advanced technologies such as artificial intelligence and cloud native. More importantly, the platform formed by the combination of these tools In fact, there is no overall consideration from the beginning of the architecture, so it is difficult to integrate and provide a comprehensive solution that is compatible with each other.

These are all obstacles to the pursuit of faster, stronger, and simpler chip design, and also a major obstacle to the industry’s choice of localized tools. Therefore, the EDA technology of new enterprises must be fully advanced, innovate on the underlying framework, support multiple processor architectures; support cloud native, artificial intelligence and other technologies; most importantly, must be innovative in methodology.

Indeed, verification occupies a lot of time and cost. TC.Lin, the chief scientist of Xinhua Zhang, quoted an IBS report and pointed out that the cost of chip design is mainly two pieces: functional verification and software development. Among them, the bottleneck of verification affects the entire design cycle-before the pre-requirement definition and RTL synthesis, a complete verification of the high-level design is required; after the RTL is written, the final circuit is generated through synthesis and placement and routing, and Both of these tools may also cause functional errors, so verification must be done again; after the chip is taped out, it is necessary to make sure that all the processes meet the design requirements, and post-silicon (post-silicon) verification is required. The whole process is time consuming and laborious.

In order to reduce the cost of verification, the industry has adopted software and hardware co-verification to shorten the development cycle, that is, shift-left, the verification method in the chip design process, including system and chip, hardware and software. But this is not enough to solve the problem of high design cycle and cost. TC.Lin said that since the establishment of Xinhuazhang, in addition to the development of mainstream verification tools, it has also continued to pay attention to research and find ways to solve the above-mentioned dilemma. In the EDA 2.0 white paper released by the company, three key paths are proposed: openness and standardization, automation, intelligence, platform and service.

Recently, Xinhua Zhang has launched the latest product portfolio, which embodies several elements mentioned in the critical path of the white paper. This group of products includes a groundbreaking smart V verification platform and four new architecture EDA verification tools:

FusionVerify Platform

1+4 innovation landing domestic EDA tools breakthrough upgrade

It consists of five product series including logic simulation, formal verification, smart verification, FPGA prototype verification system and hardware simulation system, and three bases including smart compilation, smart debugging and smart verification cockpit.

The Smart V verification platform has a unified debugging system, a compilation system, an intelligent segmentation technology, a rich scene incentive source, and a unified cloud-native software architecture. It can integrate different tool technologies and provide customization for various designs and different scenarios. The comprehensive verification solution that solves the current industry compatibility challenges of individual tools and verification efficiency challenges caused by data fragmentation. Smart V verification platform can effectively improve verification efficiency and ease of use of the solution, and bring verification benefits that cannot be provided by point tools.

Huajie (HuaPro-P1)
High-performance FPGA prototype verification system

1+4 innovation landing domestic EDA tools breakthrough upgrade

Based on FPGA hardware and full-process software with independent intellectual property rights, it can help SoC/ASIC chip customers realize the automatic synthesis, segmentation, optimization, wiring and debugging of design prototypes, and can automatically realize the intelligent design process, effectively reducing user manual input and shortening the chip The verification cycle provides a new generation of intelligent pre-silicon verification system with large capacity, high performance, automatic implementation, debuggability, and high availability for system verification and software development.

Dome (GalaxSim-1.0)
Digital simulator

1+4 innovation landing domestic EDA tools breakthrough upgrade

Use the new software architecture to provide multi-platform support, support different processor computing platforms, such as X86, ARM, etc., and have been tested on multiple domestic architectures based on the ARM platform. It can be combined with the universal debugger and universal coverage database of the Xinhuazhang’s Dome GalaxPSS intelligent verification system, and the Dome simulator can efficiently cooperate with other verification tools to provide a unified data interface. It supports IEEE1800 SystemVerilog grammar, IEEE1364 Verilog grammar, and IEEE1800.2 UVM methodology. It has reached the level of mainstream commercial simulators in terms of semantic analysis, simulation behavior, and timing models.

Dome (GalaxPSS)
A new generation of intelligent verification system

1+4 innovation landing domestic EDA tools breakthrough upgrade

Based on the fusion of Accellera PSS standard and advanced verification methodology, for current and future complex verification scenarios, scenarios are automatically generated, reducing the reliance on the experience of engineers manually writing scenarios, generating more efficient test scenarios and test incentives for the chip, and improving verification Scene coverage and completeness. The code generated by PSS is portable, which can ensure that it is suitable for software simulation, hardware simulation, FPGA prototype verification, and even system verification, providing from single-platform verification to multi-platform interactive verification.

Qionghan (GalaxFV)
The domestic EDA field takes the lead in an extensible formal verification tool based on word-level modeling

1+4 innovation landing domestic EDA tools breakthrough upgrade

It adopts high-performance word-level modeling (Word-Level Modeling) method to build, with high performance, high scalability, friendly expansion interface, the model has reached the international advanced level. Equipped with a high-concurrency and high-performance solver, an intelligent scheduling algorithm engine, and a dedicated assertion library, it can make full use of computing power and improve parallel efficiency, while effectively improving ease of use and use efficiency, lowering the threshold for formal verification in the industry .

The future digital system will be a deep integration of system + chip + algorithm + software. In less than two years, Xinhuazhang has developed the above products from scratch, laying a solid foundation for a more intelligent system design process. Wang Libin said that the release of the new platform and products will have far-reaching significance not only for the Xinhua chapter, but also for the entire EDA industry and integrated circuit design industry.

At present, these tools have been used in the chip design of companies such as the Institute of Semiconductors of the Chinese Academy of Sciences, Feiteng, Haiguang, Zhanrui, and ZTE Microelectronics. Ding Wenwu, president of the National Integrated Circuit Industry Investment Fund, said that since its establishment, Xinhuazhang has continued to innovate and forge ahead and has become a new backbone enterprise in the field of digital verification in China. Shen Changxiang, an academician of the Chinese Academy of Engineering, said that Xinhuazhang launched a high-performance integrated circuit design tool with independent intellectual property rights and supporting domestic computer architecture servers within two years of its establishment. R&D work provides more choices and promotes the safer development of the domestic integrated circuit industry chain. Ye Tianchun, National 02 Special Technology Chief, also congratulated Xinhuazhang’s new digital EDA verification product on the market. He also said that for China, the next few years will usher in a great opportunity for the development of domestic EDA tools.

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