Cadence unveils latest AWR Design Environment platform



Cadence unveils latest AWR Design Environment platform

Cadence unveils latest AWR Design Environment platform

Cadence Design Systems has unveiled the AWR Design Environment Version 16 (V16) which offers cross-platform interoperability to support RF to mmWave intellectual property (RF IP) integration.

It is intended for heterogeneous technology development across the Cadence Virtuoso design platform as well as the Allegro PCB and IC package design platforms.

The V16 release has introduced seamless integration with the Clarity 3D Solver and Celsius Thermal Solver, delivering unlimited capacity for electrothermal performance analysis of large-scale and complex RF systems. The AWR Design Environment, including Microwave Office circuit design software, helps customers to design 5G wireless and connected systems more efficiently for automotive, radar systems, and Semiconductor technologies. According to Cadence, platform and solver integration in the V16 release provides up to a 50% reduction in turnaround time (TAT) compared to competing workflows.

“To win today in the highly competitive 5G/wireless markets, customers are demanding solutions that enable complete and comprehensive RF workflows that don’t just start and stop at the chip but extend to the entire system,” said Vinod Kariat, corporate vice president of research and development at Cadence. “The RF workflow innovations enabled by the AWR Design Environment V16 release start with a foundational advance in the way design data and software IP are now shared and seamlessly transferred across products. Under the overarching Cadence umbrella, the level of RF integration being introduced with this release is truly an advancement for engineering team productivity.”

Platform interoperability is crucial to accelerating RF integration and promoting engineering productivity and by seamlessly sharing design data among the AWR Design Environment, Virtuoso, and Allegro platforms it is now possible to eliminate any disconnect between RF design and manufacturing layout teams, saving engineering resources and positively impacting development schedules.

With the V16 release and its deep electromagnetic (EM) and thermal embedded analyses, customers are seeing more than a 3X reduction in TAT.