Capacitorless 3D DRAM

Imec has developed  a fully 300mm BEOL compatible IGZO-based capacitorless DRAM cell with >103s retention and unlimited (>1011) endurance.

These results were obtained after selecting the most optimal integration scheme for the single IGZO transistors, i.e., a gate-last integration scheme with buried oxygen tunnel and self-aligned contacts.

The implementation of a buried oxygen tunnel in combination with an anneal in O2 ambient was proven to reduce the oxygen-vacancy concentration in the IGZO channel without impacting the series resistance at source and drain region – leading to larger on-current and lower off-current.

With this architecture, the gate length of the IGZO TFT could be scaled down to an unprecedented 14nm, while still preserving >100s retention.

The retention at small gate length could be further optimized by controlling the threshold voltage (Vt) through equivalent oxide thickness (EOT) scaling, by contact resistance improvement and by reducing the IGZO layer thickness.

When the latter thickness is reduced to 5nm, the oxygen tunnel and anneal step in O2 can even be omitted – leading to a much-simplified integration approach.

 

Capacitorless 3D DRAM

Figure 1: (a) Schematic and (B) TEM image of a single IGZO Transistor in a gate-last architecture with oxygen tunnel, and 14nm gate length.

So far, an accurate model for predicting the IGZO-based DRAM lifetime is lacking since the IGZO TFT’s degradation mechanisms are not fully understood. IGZO transistors are inherently n-type devices, and this points to positive bias temperature instability (PBTI) as possibly the main degradation mechanism.

PBTI is a well-known aging mechanism in Si n-type metal-oxide-Semiconductor field-effect transistors (mosfets) where it can severely affect the device performance and reliability.

It typically manifests itself as an undesirable shift of the device threshold voltage and a decrease of the drain current. For these Si-based devices, PBTI is ascribed to the presence of electron traps in the gate dielectric, trapping charge carriers from the device conduction channel.

Most of the existing reliability assessments on IGZO TFTs neglect however the impact of the gate dielectric. Imec has for the first time studied the impact of the gate dielectric on the PBTI of IGZO TFTs. The results are summarized in the 2021 IEDM paper ‘Understanding and modelling the PBTI reliability of thin-film IGZO transistors’, by A. Chasin et al.

The team found that four different mechanisms play a role in the degradation process, each with different time kinetics and activation energies. They can be mainly ascribed to both electron trapping in the gate dielectric, and to the release of hydrogen species from the gate dielectric into the IGZO channel during PBTI stress.

Capacitorless 3D DRAM

Figure 2: Time to failure for IGZO TFTs (with 12nm thick amorphous IGZO film) based on different gate dielectrics. Gate-dielectric optimization enables substantial lifetime enhancement from about 20 days to about one year at operating conditions as shown in the figure. Ultimate target is a time to failure of 5 years l. 

The imec team has combined these multiple degradation mechanisms into a model, which makes it possible to predict the IGZO TFT lifetime at target operation conditions. The model is found to fit to experimental data and can be used to propose optimizations for enhancing the lifetime.

For example, by reducing the gate dielectric thickness, the predicted time to failure can be enhanced from about 20 days to about one year.