“When using modern broadband data converters, managing the resulting high-speed serial data stream is a huge challenge. ESIstream is an open source serial data interface protocol with extremely low cost, supports simple hardware implementation of multiple FPGA architectures, and occupies minimal resources. Simply put, it is an open source alternative to JEDEC’s JESD204B subset 1 and 2 standards. In addition, ESIstream can bring many benefits to users, some of which will be discussed here, including low complexity, low link latency, and simple solutions to achieve deterministic latency.
When using modern broadband data converters, managing the resulting high-speed serial data stream is a huge challenge. ESIstream is an open source serial data interface protocol with extremely low cost, supports simple hardware implementation of multiple FPGA architectures, and occupies minimal resources. Simply put, it is an open source alternative to JEDEC’s JESD204B subset 1 and 2 standards. In addition, ESIstream can bring many benefits to users, some of which will be discussed here, including low complexity, low link latency, and simple solutions to achieve deterministic latency.
This article will only describe the architecture of ESIstream, because there are currently many documents that describe the JESD204B standard well. Then we will reveal the subtle differences between these two protocols, and introduce Teledyne e2v, the developer of the ESIstream protocol, has decided to release its own ESIstream VHDL IP to further simplify the use of users.
Since the new millennium, the development of data converter technology and CMOS technology has begun to reach a functional bottleneck. At first, high-speed ADCs and DACs (fs> 10 MHz) used parallel data interfaces, which meant that a large amount of wiring had to be drawn/introduced from each data converter on the printed circuit board (PCB) (Figure 1). As the sampling rate and output data rate increase, PCB design becomes more and more challenging. The serialized interface, initially using LVDS (low-voltage differential model), recently used the serializer/deserializer (SERDES) interface (the clock is embedded in the data stream), which provides a solution to this data transfer challenge It can simplify PCB wiring and greatly promote the development of shape parameters. This simplification of the interface is beneficial to both ends of the link (Figure 1). The Serdes link further simplifies the design of the PCB because there is no need to ensure that the length of the data line matches.
Figure 1 How a serial link reduces interconnection load.
However, after many years, there is a serial solution to solve all the system-level challenges brought by broadband data converters. Achieving deterministic delay is a prerequisite for simultaneous sampling, and people have paid a lot of effort to study it. The following table (Table 1) shows the development of the JESD204 standard and the development of the open source ESIstream in the past 12 years or more.
The point is that the encoding/decoding process is introduced, and the alignment between the paths is compensated by some additional receiving path elastic buffers, resulting in an additional transmission delay.
Figure 2 Serialization introduces interconnection delay.
Serialization can also help manage the power requirements of data converters because it can reduce the number of specific output drivers required by a single device. Moreover, by implementing a differential serial line, it can help reduce the electrical noise generated in a complex system to ensure a good dynamic range. In addition, the coding scheme can also disperse spectral noise, and the differential signal can reduce crosstalk.
In fact, until now, the early serial interface still does not support the application of multiple parallel channels well, and designers still face the challenge of board-level design.
ESIstream specific implementation
Now let us look at the core elements of ESIstream. ESIstream uses 14b/16b data encoding algorithm, with the least significant bit first, and supports line rates exceeding 13 Gbps. It supports 12-bit and 14-bit converters. The protocol uses linear feedback shift register scrambling technology, adding unequal bits and clock synchronization bits (an extra burden of 2 bits) to each data word, as shown in Figure 3. In this way, its encoding efficiency is as high as 87.5%, which is slightly higher than JESD204B (8b/10b encoding stream). The unequal bit (DB) can maintain the DC balance between the data chains when the CLK bit is switched to enable synchronous monitoring.
Figure 3 ESIstream basic data frame
The upper-layer block diagrams of the ESIstream transmitter (Tx) and receiver (Rx) cores are shown in Figure 4 and Figure 5.
Figure 4 Tx path of ESIstream
Figure 5 Rx path of ESIstream
The ESIstream encoding algorithm is designed to reduce the physical limitations of the serial interface. Most importantly, the link between the transmitter and receiver requires AC coupling. With this in mind, the transmitted data must ensure DC balance, otherwise the link coupling capacitor may drift, causing the data eye diagram to close and destroying the received data.
At the receiving end, the clock and data recovery (CDR) module usually uses a PLL to lock to the transmitted signal, so there is no need to use a separate clock line. However, in order for the CDR to lock and maintain the locked state, it is necessary to ensure that the transmitted signal undergoes a specific number of transformations.
The purpose of scrambling the sent data is to maintain DC balance and ensure that the link remains locked. The developers of ESIstream wanted to limit the complexity of the digital design, so additional algorithms were used to minimize error transmission. This algorithm is based on the Fibonacci sequence with a length of 217-1. In addition, a 14-bit shift is applied. The useful data output by the conversion process and the linear feedback shift register data (pseudo-random code) are XORed, as shown in Figure 6.
Figure 6 Realize data scrambling by XOR with LSFR code
After scrambling, the 14-bit data result is encoded into a 16-bit data frame. The first additional bit clock bit switches with each successive frame. The second additional bit unequal bit is set according to the current state of the unequal counter (RDC). Two RDC states can lead to:
1. RDC is less than +/-16, and the unequal bit is set to ‘0’.
2. RDC is greater than +/-16, the unequal bit is set to ‘1’, and the data is reversed (bitwise NOT operation).
This operation can meet the requirement of the minimum number of conversions locked by the Rx PLL and meet the requirement of link DC balance. Under normal operation, the receiving end first checks the unequal bit. If it is high, the received data is reversed before descrambling. If it is low, the data will be descrambled directly.
For deterministic operations, ESIstream requires link synchronization, that is, the data frames of the transmitter and receiver are aligned, and the scrambling engines at both ends of the link are in the same initialization state. Synchronization is divided into two steps, frame alignment and pseudo-random bit sequence (PRBS) initialization.
Figure 7 ESIstream link synchronization frame
The receiving end initiates the process by enabling SYNC. This pulse should last at least one frame period. Then the transmitter sends a 32-frame alignment pattern (Figure 7). At the receiving end, this reserved sequence bypasses the scrambling and unequal processing, so that the timing of the receiving end and the transmitting end are aligned.After aligning the frames, the transmitter immediately sends a 32-frame PRBS data-including 14 bits
PRBS and clock and inequality information. After correct processing, the receiving end LFSR is initialized by the receiving end PRBS word. The link is now synchronized (Figure 8). The user can continuously monitor the synchronization status by observing the clock bit at the receiving end. If the clock bit is not switched in a certain frame, a synchronization problem has occurred, and the link needs to be reset and resynchronized.
Figure 8 ESIstream receiver line synchronization sequence
Through scrambling and processing of clock bits and unequal bits, ESIstream can guarantee certain data transmission.
Synchronous GHz sampling system-not for the faint-hearted
The application of digital beamforming in a radio system requires simultaneous sampling of the low-level signals of the antenna array. This requires saving the spatial information of the signal reaching each antenna node. Although this solution is more complex and will bring additional power consumption, it also has some significant advantages:
・ High signal-to-noise ratio (SNR) helps increase wireless link capacity, thereby increasing signal range
・ Use the spatial characteristics of the antenna array to avoid interference. Because the interference comes from a certain direction, the beamforming algorithm can use nulling techniques to eliminate the interference.
・ High-efficiency and large-capacity wireless links mean that the radar system can track multiple targets at the same time, or the mobile phone network can support multiple calls.
Today, many applications use beamforming, or at least require simultaneous sampling. However, when working at GHz frequencies, the propagation time of the IC and board-level signals is very important. PCB traces are used for transmission lines, so it is necessary to ensure that the signal line lengths match to maintain phase information. Each centimeter of the line length will increase the delivery time by 60 to 75ps. Comparing it with the 166ps clock period of the 6GHz sampling clock, it can be seen that the board-level effect will greatly affect the design. This explains why PCB layout is a key factor in high-speed sampling systems. However, there is another factor that makes the design difficult. This factor is related to the time domain and is called metastability.
Synchronization chain brings definite delay to ESIstream
Metastability describes an uncertain state in digital circuits. As the sampling rate increases, it becomes an important cause of potential system timing problems. Users need to use synchronization methods to combat metastability, which is the reason for the introduction of the synchronization chain scheme.
The user needs a reliable and simple method for realizing synchronization timing. In Teledyne e2v, deterministic synchronization is built around a pair of event-driven differential electrical signals: synchronization and synchronization output signals (SYNCTRIG and SYNCO). These signals ensure that the timing system of the target converter can be reset and all digital subsystems are properly locked to the master reference clock. In addition, this synchronization scheme can be extended to multiple ADCs in large systems.
The advantage of this scheme is that it is very simple-it does not require an additional clock signal, and can ensure the synchronization of multiple parallel channels during the life cycle of the system. Once the design is complete and ready for production, a training sequence can be used to establish correct system synchronization. If the environmental conditions change, such as temperature or voltage changes, the system timing parameters remain unchanged. The synchronization chain provides a very reliable synchronization source, which is a huge advantage for mass production of products.
Then, in order to achieve deterministic delay, there is a simple counter and receiving elastic buffer at the receiving end of the ESIstream link to compensate for the uncertainty of the maximum line delay in the transmission process.
Figure 9 The position of the frame counter in the ESIstream receiver
The counter module inside FPGA counts the number of Rx clocks between the SYNCTRIG rising edge event and the “all lines ready to receive” event. This information and the flexible receiving buffer allow alignment of the received data of the entire system. In this way, it is feasible to use the signal chain function of ESIstream’s products to extend deterministic behavior to the entire system using ESIstream.
ESIstream VHDL module-development goals
In order to make ESIstream easier to use, Teledyne e2v, the creator of Teledyne e2v, launched a project at the end of 2018 to develop ESIstream Tx and Rx IP modules for general FPGAs provided by FPGA manufacturers in the industry (including Xilinx and Intel). IP will support different operating speeds and be suitable for applications of different levels including aerospace-grade. Undoubtedly, the focus of IP is to provide matching performance to Teledyne e2v’s existing product line. In order to realize this fixed-function IP, Teledyne e2v has done a lot of work on the bottom layer to dynamically define configurable line rate modules, including a wide range of data converter sampling frequencies, and supporting more definable functions.
The future of serialization
Teledyne e2v’s future development plan also includes fiber optic applications for the ESIstream physical layer. Optical fiber allows the converter to be placed far away from the FPGA instead of a copper-based interface (PCB trace or coaxial cable). By connecting two Xilinx VC709 evaluation boards using four SFP (Small Pluggable) optical lines and running at a speed of 6Gsps, the above characteristics are proved.
Figure 10 Fiber demonstration using physical layer ESIstream Tx and Rx
After complete testing and certification, the VHDL code module will be placed on the website for users to download for free.
Comparison of ESIstream and JEDEC
The system-level advantages of ESIstream can be briefly summarized as follows:
・The LMFC clock of each device is not required, and the alignment operation of the LMFC clock is not required.
・When using a single device or using a synchronization chain to synchronize multiple devices, there is no need to consider the PCB line length matching of the ESIstream synchronization signal.
・No SYSREF is required, so compared with JESD204B, ESIstream reduces hardware complexity and achieves deterministic operation.
・The definite synchronization behavior in the ESIstream system is achieved through a feature called synchronization training (please refer to other documents). ESIstream only requires one system training. Once the delay parameters are obtained, these delay parameters will remain unchanged for a given design. This means that ESIstream is an interface that is easy to mass produce.
The JEDEC data serialization method described in JESD204B subsets 1 and 2 seems to solve the challenge of deterministic operation of multi-channel data converter systems. This is undoubtedly correct to a certain extent, but what is usually overlooked are the many challenges that designers encounter when dealing with complex transmission and specification physical layer requirements. Engineers generally believe that the JESD204B license and core IP for signal processing SoCs (FPGA or ASIC) can help solve most design problems. However, according to reports, many facts and experiences show that the timing constraints of multi-domain clock complexity introduced by JESD204B have brought great trouble to PCB design.
There is another way. ESIStream. ESIStream is an open source and free protocol. It has the same performance level as JESD204B, but can bring a better user experience. Low complexity, easy to design, low power consumption. Now, with the release of Rx and Tx IP modules and VHDL code modules for industry standard FPGAs, the difficulty of using ESIstream has been greatly reduced. Currently, the IP module is in the development stage and will support the specifications of Teledyne e2v’s new data converter. In addition, users can download VHDL code modules suitable for their own high-speed serial projects for free.