Want to avoid interrupting the data flow?Give you a different synchronization method Distributed Systems

In a stand-alone design, the local clock or oscillator used will itself be synchronized. However, when the independent design needs to be integrated into a wider system (we call it a distributed system), the perspective of the problem will change, and the independent system should also be designed according to the use case.

To calculate the instantaneous power consumption of appliances in a system, current and voltage must be measured at the same time. Through quick analysis, you can solve the problem in three different ways:

Use two simultaneous single-channel ADCs to measure current and voltage.

Using a multi-channel simultaneous sampling ADC, each of its channels may have an ADC, or each channel may have a sample-and-hold circuit.

Use a multiplexed ADC and insert measurements to compensate for the time shift between voltage and current measurements.

At this point, you may have obtained a reliable solution that can solve the problem, but if we expand the system requirements, from the original single piece of electrical radiation to the entire application, we must measure the power of each AC power outlet in the entire factory? Now, your original instantaneous power consumption design must be distributed and applied to the entire factory, and you must ensure that its design can measure and calculate the power consumption of each AC power outlet at the same time.

What you are facing is a distributed system, which consists of a set of independent but closely related subsystems. Each subsystem needs to provide data sampled at the same time point in order to calculate the instantaneous total power consumption of the plant.

Finally, if we continue to expand the hypothetical application example, imagine if you want to integrate your original design into the national grid. Now, what you are testing is millions of watts of power. Any link failure will lead to terrible consequences, such as line damage due to pressure. In turn, this may cause power outages and cause terrible consequences, such as fires or power outages in hospitals. .

Therefore, all systems must be accurately synchronized, that is, the data captured in the entire power grid must be captured at the same time, regardless of the geographic situation of each data, as shown in Figure 1. Figure 1. Grid synchronization.

In these cases, you can think of it as a critical distributed system, and you must obtain a continuous, fully synchronized data stream from each sensor node.

Similar to the grid example, these requirements also apply to many other critical distributed system examples in the aerospace or industrial markets.

Before beginning to explain how to synchronize the sampling moments of multiple ADCs, it is best to understand how each ADC topology decides when to sample the analog input signal, as well as the advantages and disadvantages of each architecture.

Nyquist or SAR ADC: The maximum input frequency of this converter is determined by the Nyquist or half sampling frequency.

Oversampling or ∑-? ADC: The maximum input frequency is generally proportional to the maximum sampling frequency, which is generally about 0.3.

On the one hand, the input signal sampling time of the SAR ADC is controlled by an external pulse applied to the conversion start pin. As shown in Figure 2, applying a common conversion start signal to each SAR ADC in the synchronized system will trigger sampling at the same time on the edge of the conversion start signal. As long as it is ensured that there is no obvious delay between the signals, that is, the conversion start pulse arrives at each SAR ADC at the same time in time, system synchronization is easy to achieve. Note that the propagation delay between the pulse arriving at the conversion start pin and the actual sampling time cannot be different from device to device. In a precision ADC with a relatively slow sampling speed, this delay is not significant.

At a certain time after the conversion start pulse is applied (also called conversion time), the conversion result will be Displayed through the digital interface of all ADCs. Figure 2. Synchronous distributed system based on SAR ADC.

On the other hand, due to different architectures, Σ-? ADC operation is slightly different. In this type of converter, the internal core (that is, the modulator) samples the input signal at a higher frequency (modulator frequency, fMOD) than the minimum frequency specified by Nyquist, so it is called an oversampling ADC.

By sampling at a higher frequency than strictly required, more samples can be collected. Then use the averaging filter to post-process all ADC data for two reasons:

For every 4 average samples, the noise is reduced by 1 bit.

The average filter transfer function is a low-pass filter. When the ∑-? architecture pushes its quantization noise to high frequencies, the average filter transfer function should be removed, as shown in Figure 3. Therefore, this filtering is completed by this average filter. Figure 3. ∑-? Noise shaping.

The average number of samples, that is, the decimation rate (N), will determine the output data rate (ODR). The output data rate is the rate at which the ADC provides the conversion result, in units of samples per second, as shown in Equation 1. The decimation rate is usually an integer, with a set of predefined values ​​that can be discretely programmed on the digital filter (ie N = 32, 64, 128, etc.). Therefore, by keeping the fMOD constant, the ODR will be configured according to the N value in the predefined value set. The averaging process is usually implemented internally by a sinc filter, and the analog conversion start pulse of the modulator is also generated internally, so the conversion process is not triggered from an external control. This type of converter will actually continuously sample, track the input signal, and process the obtained data. Once the process (sampling and averaging) is completed, the converter generates a data ready signal to inform the controller that the data can be read back through the digital interface. As shown in Figure 4, the work flow of ∑-? can be summarized into four main steps:

The modulator samples the signal at the fMOD frequency.

The samples are averaged through a sinc digital filter.

Perform offset and gain corrections on the data provided by the sinc filter.

The data ready pin is switched to indicate that the conversion result is ready and can be read back by the controller. Figure 4. ∑-? ADC working flow chart.

Since there is no external control when to trigger internal sampling, if you want to synchronize multiple ∑-? ADCs in a distributed system, you must reset all digital filters at the same time, because the average conversion is started by the digital filter. controlling. Figure 5 shows the impact on synchronization when all Σ-? ADCs use the same ODR and fMOD.

Figure 5. ∑-? System reset synchronization

As with the SAR ADC-based system, it must be ensured that the reset filter pulse reaches each subsystem at the same time.

However, please note that every time the digital filter is reset, the data flow will be interrupted because the filter must be reset. In this example, the duration of the data interruption is determined by the order of the digital filter, fMOD, and decimation rate. In the example shown in Figure 6, the LPF characteristic of the filter will delay time until a valid output is generated. Figure 6. Data interruption due to the settling time of the digital filter.

Enlightenment for Synchronous Sampling in Distributed System

In a distributed system, the global synchronization signal (we call it Global_SYNC) is shared among all modules/subsystems. This synchronization signal can be generated by the main system or a third-party system (such as GPS 1 pps), as shown in Figure 1.

After receiving the Global_SYNC signal, each module must resynchronize the instantaneous sampling of each converter (probably its local clock) to ensure simultaneity. In a SAR ADC-based distributed system, resynchronization is inherently simple, as described in the previous section: the local clock (management conversion start signal) matches the Global_SYNC signal again, and then the signal is synchronized to obtain the signal.

This means generating frequency spurs, because during synchronization, a sample is collected at a different time and distance, as shown in the highlighted blue part of Figure 7. In distributed applications, these spurs may be acceptable, and interrupting the data flow is indeed critical in some applications, such as the aforementioned power line monitoring applications. Figure 7. Adjust the SAR ADC conversion process to match the global synchronization signal.

In a ∑-?-based distributed system, the process of resynchronizing with the Global_SYNC signal will be slightly more complicated, because the modulator will continue to sample the analog input signal, and the conversion process is not controlled externally like a SAR ADC.

To synchronize multiple distributed systems based on Σ-?, a simple method is to reset the digital filter: discard all collected and stored modulator samples to be used on the averaging filter, and clear the digital filter. This means: According to the order of the digital filter, it will take some time to determine its output again, as shown in Figures 5 and 6.

After the digital filter is set, it will provide valid conversion data again, but considering the time it takes to set, the data interruption that may be caused by resetting the digital filter on the Σ-? ADC is unacceptable. The higher the frequency that the distributed system needs to be resynchronized, the more the number of data flow interruptions, and because of this continuous data flow interruption, Σ-? ADC will not be able to be used in key distributed systems.

The traditionally used method to minimize data interruption is to use a tunable clock, such as a PLL, which can reduce the error between the global synchronization frequency and the fMOD frequency. After receiving the Global_SYNC pulse, a process similar to the following can be used to calculate the uncertainty between the start of the ∑-? ADC conversion and the Global_SYNC pulse:

The controller calculates the time difference between the sampling moment (calculated backward from the data ready signal by knowing the group delay, as shown in Figure 8) and the Global_SYNC pulse. The group delay is a data sheet specification that describes the time interval from when the input is sampled to when the data ready pin is turned on (indicating that the sample is ready and can be read). If there is a time difference between the sampling instant and Global_SYNC, the local controller will quantify the time difference (tahead or tdelayed), as shown in Figure 9. Figure 9. Quantify the time difference between the sampling instant of each ADC (assuming the group delay is known) and the global synchronization signal.

If there is a difference, you can reset the ∑-? filter, or modify the fMOD to adjust the ∑-? sampling during a few sampling periods. In either case, several samples may be missed. Note that by changing the local clock frequency (fMOD), the ∑-? ADC will change its output data rate (ODR = fMOD/N). In this way, the ADC will slow down or speed up the sampling speed of the analog input, in order to reduce the impact of the rest of the system. ADC and Global_SYNC are synchronized.

If fMOD is updated, then after synchronization, the main clock frequency will be restored to the original frequency to return to the previous ODR, and the subsystem will synchronize from this moment.

The process of changing fMOD over a period of time is shown in Figure 10. Figure 10. Synchronization method, using PLL to tune the frequency of the modulator.

This method may not be applicable in some situations, because there are several details to consider:

It may not be practical to change the modulator frequency to a non-integer multiple.

If the frequency can be fine-tuned, the changed frequency step must be small, otherwise the digital filter may exceed the limit, resulting in a longer synchronization implementation time.

If the required ODR change is large enough, it can be solved by changing the decimation rate (N) instead of changing the modulator frequency (fMOD), but this also means that some samples will be lost.

Using a PLL means that in addition to its own settling time, additional power will be consumed before the desired modulator frequency is reached.

Generally speaking, the complexity and cost of the entire system will increase with the increase of the system scale, especially compared with SAR ADC. For the latter, only need to adjust the conversion to match the Global_SYNC signal, and it can be easily solved this problem. In addition, in many cases, sigma-? ADCs cannot be used because of the above-mentioned system limitations.

Without interrupting data, easily resynchronize ∑-? ADC

AD7770 series products (including AD7770, AD7771 and AD7779) have built-in SRC. With the introduction of this new architecture, the limitation caused by the fixed decimation rate (N) will no longer exist.

SRC allows you to use a decimal number (not just an integer) as the decimation rate (N), so you can use any output data rate you want. In the previous synchronization method, since N is fixed, the external clock must be changed to adjust fMOD before synchronization can be implemented.

After using AD7770 series products, N will become a flexibly programmable value and a value that can be programmed at any time, so ODR can be programmed without changing fMOD or interrupting data. This new method of resynchronizing a Σ-?-based subsystem utilizes SRC to simplify the resynchronization process and simplifies the complexity mentioned in the previous chapter to the greatest extent.

The new method is as follows:

After receiving the Global_SYNC signal, each subsystem checks whether the sampling is synchronized, using the data ready signal as a reference, and using the group delay to find the actual sampling time.

If there is a time difference between the sampling moment and the time when the Global_SYNC signal is received, the local controller will quantify the time difference (tahead or tdelayed) as shown in Figure 9.

At this time, a new ODR is programmed to change the decimation rate (N) through the SRC, thereby temporarily generating a faster or slower ODR. The entire resynchronization operation generally uses 4 samples (if the sinc5 filter is enabled on the AD7771, 6 samples are required), but because these samples are still valid and fully set, they will not cause the data flow to be interrupted.

Once the required number of DRDY is received, the decimation factor will be reset to return the required ODR, so that the ∑-? ADC can be synchronized with the rest of the subsystems, as shown in Figure 11, which does not cause data interruption.

Figure 11. The sampling rate converter dynamically adjusts the ODR to resynchronize sampling on all devices.

8-channel, 24-bit simultaneous sampling analog-to-digital converter (ADC)

Single-ended or true differential input

Each channel has a programmable gain amplifier (PGA, gains of 1, 2, 4, and 8)

Low DC input current: ±8 nA

Output data rate (ODR) per channel up to 32 kSPS

Programmable ODR and bandwidth

Sampling rate converter (SRC) for coherent sampling

Sampling rate resolution up to 15.2 × 10? 6 SPS

Low delay sinc3 filter path

2.5 V internal reference voltage source

Two power consumption modes:

High resolution mode

Low power mode

in conclusion

Critical distributed systems require all subsystems to be converted synchronously and have a continuous data flow. The SAR converter provides an intuitive resynchronization sampling method: by re-adjusting the conversion start signal to match the Global_SYNC pulse.

In applications that require high dynamic range (DR) or signal-to-noise ratio (SNR), SAR cannot be used, but traditional ∑-? converters have also become difficult to use because these converters are not flexible and cannot be used without interrupting data. Readjust in case of flow.

As the example shows, SRC provides a seamless synchronization routine, which has lower latency, lower cost, and lower complexity than other solutions.

SRC can show its strengths in many applications. As with the power line monitoring example, any line frequency change can be compensated by immediately dynamically changing the decimation rate. In this way, it is ensured that the sampling frequency of the power line is always consistent. As shown in this article, in critical distributed systems, SRC can also be used to efficiently resynchronize the system without interrupting the data flow and without the need for additional components such as PLL. AD7770 solves the traditional problem of synchronizing distributed systems based on ∑-? ADCs, without losing samples, and without adding additional cost and complexity like PLL-based methods.