Weebit completes design and tape-out of embedded ReRAM module
Weebit Nano, a developer of next-generation Semiconductor memory technologies, has completed the design and verification stages of its embedded ReRAM module.
The company also confirmed that it had taped-out (released to manufacturing) a test-chip that integrates this module, which will be used as the final platform for testing and qualification, ahead of customer production.
Memory modules are a critical component when embedding a memory array in a System-on-Chip (SoC) and act as the interface between the memory array and the rest of the system and includes the logic that controls the way the array is accessed.
The test chip comprises a full sub-system in which the module is embedded. It also includes a RISC-V microcontroller (MCU), system interfaces, Static Random-Access Memory (SRAM) and peripherals. Potential customers can use it as a development and prototyping platform for new products such as low-energy Internet of Things (IoT) devices.
Commenting Weebit’s CEO Coby Hanoch said, “We implemented the module in an intelligent way, developing unique patent-pending analogue and digital smart circuitry that significantly enhances the array’s technical parameters including speed, retention, and endurance. The test chip containing this module will allow Weebit to demonstrate to customers a fully functional ReRAM product that can be readily integrated into their System-on-Chip and enable customers to accelerate their design process.”
ReRAM has the potential to enable tighter system integration and lower power consumption, even at high junction temperatures.
Weebit’s new memory module can be easily customised and has been designed to provide a foundation for the company’s future ReRAM compiler, which will enable customers to automatically reconfigure the design according to their specific requirements without going through exhaustive manual design and fab qualification processes. The module will also be the basis for other ReRAM modules that Weebit will develop, tape-out and qualify at production fabs based on customer requests starting later this year.
According to Weebit, the ReRAM module was designed in the ST 130nm process after interaction with potential customers showed it is the sweet spot for their analogue, power, sensor and IoT designs. It includes a 128Kb ReRAM array, control logic, decoders, IOs (Input/Output communication elements) and error correcting code (ECC).
Weebit said that it expects to have its first silicon of the embedded ReRAM module towards the end of 2021.